X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture

We present X-tolerant deterministic BIST (XDBIST), a novel method to efficiently compress and apply scan patterns generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. Our method allows test patterns to have any number of unknown values with no degradation in compression and application efficiency. XDBIST does not require changing the core logic of the device under test (DUT); no test points or X-blockage logic need be inserted. The proposed solution guarantees the same high test coverage and diagnosis ability as deterministic scan-ATPG and uses the same tester flow, while reducing test data volume and tester cycles by more than 10 times.